The present invention relates to a semiconductor data processing device having electrically erasable and writable nonvolatile memory cells, more specifically, to a technique for erasing the nonvolatile memory cells. For instance, the present invention relates to a technique effective to be applied to a flash memory or a microcomputer over which the same is mounted.
Patent Reference 1 describes a technique in which a flash memory array is divided into sectors to sequentially perform erase for each of the sectors, and before completely erasing the memory cells in one sector, erase of the memory cells in another sector is started to shift erase of the sectors in time for distributing a peak current at erase.
Patent Reference 2 describes a technique in which a flash memory array is divided into blocks to sequentially perform application of an erasing voltage for each of the blocks, thereby distributing a peak current at erase.
Patent Reference 3 describes a technique in which a chip has a plurality of memory arrays, erase is performed plural times for time division erase, thereby distributing a peak current at erase. The memory arrays are erased together. The memory arrays are divided into groups which are erased together. The number of memory arrays in the group is increased corresponding to the progress of erase to shorten erase time.
Patent Reference 4 describes a technique in which a memory array is divided into blocks to perform time division erase for each of the blocks, thereby distributing a peak current at erase. At erase, erase verify is performed for each of the blocks, thereby preventing over erase.
Patent Reference 5 describes a technique in which a memory array is divided to perform time division erase for each division, thereby distributing a peak current at erase for preventing the erasing voltage level from being lowered and for reducing the load of an internal booster circuit.
Patent Reference 6 describes a technique in which a memory array is divided into blocks, part or all of the memory array has a plurality of subdivided blocks to perform erase for each of the subdivided blocks, thereby distributing a peak current at erase.    [Patent Reference 1] Japanese Unexamined Patent Publication No. Hei 10 (1998)-199271    [Patent Reference 2] Japanese Unexamined Patent Publication No. Hei 6 (1994)-150677    [Patent Reference 3] Japanese Unexamined Patent Publication No. Hei 6 (1994)-103790    [Patent Reference 4] Japanese Unexamined Patent Publication No. Hei 4 (1992)-228193    [Patent Reference 5] Japanese Unexamined Patent Publication No. Hei 2 (1990)-232899    [Patent Reference 6] Japanese Unexamined Patent Publication No. Hei 3 (1991)-105795